1. Field of the Invention
The present invention relates to an integrated circuit and a test circuit for testing the integrated circuit.
2. Description of the Related Art
Conventionally, in order to test a large-scale core (portion) and its peripheral circuits used in integrated circuit devices, the core is generally isolated. In this case, it is necessary to provide access paths for directly setting (or sending) and observing test data to the core and its peripheral circuits from external terminals. There are two known methods for setting the access paths: the first one is a parallel type, in which data are provided from external terminals to core terminals in a one-to-one correspondence relationship (refer to Japanese Unexamined Patent Application, First Publication, No. Hei 11-202031), and the second one is a serial type, in which data are serially sent from a single external terminal via a scan (or scanning) path (refer to Japanese Unexamined Patent Application, First Publication, No. Hei 10-78475).
The above publication Hei 10-78475 discloses a method of testing the core of a RAM (called “RAM core”, hereinafter), to which the serial method is applied. In the method, each input terminal of the RAM core is connected to a scan path having three scan flip-flops (abbreviated to “input FF side”, hereinafter), and similarly, each output terminal of the RAM core is connected to a scan path having three scan flip-flops (abbreviated to “output FF side”, hereinafter). The input FF side, RAM core, and output FF side are serially connected. In order to test the RAM core in the above structure having a serial chain of the input FF and output FF sides, a test signal is input from the input FF side, and an output signal is output from the output FF side.
In this test circuit, the number of external terminals agrees with the number of scan flip-flops. Therefore, a clock signal must be input 6 times so as to repeat the shifting process, where the repetition number corresponds to the number of the flip-flops. In addition, wiring for making each signal pass through a logic circuit (i.e., user logic) is provided for each output terminal.
According to the above test method, a scan flip-flop is necessary for each terminal of the RAM core, and thus the clock signal must be input 6 times in a test. Therefore, if many terminals are provided for the RAM core, then the time necessary for executing the test will be long. In addition, the arrangement of the wiring may be complicated because the wiring for testing the core passes through the logic section.
The other publication, Hei 1-202031, discloses a parallel method of testing the core. In the disclosed circuit, a selector for selecting one of a test signal and an output signal from the core based on a test mode signal is connected to an output terminal of the first core, while a selector for outputting the test signal to an input terminal of the core or to an output terminal (connected to an external device) is connected to an input terminal of the second core. In this structure, value data are parallel-input from external terminals via the selector connected to the output terminal of the first core, while output data are parallel-output to external terminals via the selector connected to the second core. Therefore, it is necessary to provide external terminals, the number of which agrees with the number of terminals of all cores. In addition, the cores must be directly connected.
In the method disclosed by Hei 1-202031, the number of external terminals is not considered, and if many cores are used, the number of external terminals may be insufficient, resulting in the situation that tests cannot be executed. Additionally, in the above circuit arrangement, the wiring is complicated because each terminal of the cores needs specific wiring.
As explained above, in the conventional serial method, a long test time is necessary and the wiring is complicated, while in the conventional parallel method, the number of external terminals may be insufficient if the number of terminals of the cores is large, so that it is impossible to execute the test. Also in the conventional parallel method, the wiring arrangement is complicated because specific wiring is necessary for each terminal of the cores.